Reducing the size of the floating gate memory transistors to dimensions of less than 100 nm has an adverse effect on the properties of the transistor, since not all the dimensions can be reduced on the same scale. The reason for this is that the gate dielectric has to have a certain minimum thickness in order to ensure that data can be stored for a period of at least ten years.
The publication by Y. K. Choi et al.: “Sub-20 nm CMOS FinFET Technologies”, International Electron Device Meeting (IEDM) 2001 has described a FinFET with double gate. A FinFET comprises a fin or narrow web of semiconductor material which connects a source region and a drain region to one another, is provided as the channel region and is provided with a web-like gate electrode which engages over it in the style of a bridge in a transverse direction.